1. Field of the Invention
This invention relates to a data processing unit, and more particularly to a multiprocessor system employing integrated circuits. More in particular, the invention relates to a control system for accessing a fixed address (that is, an address preset in terms of hardware) in a memory unit at the time of generation of a sequence signal, for example, at the time of an interrupt, in the multiprocessor system.
2. Description of the Prior Art
In a central processing unit, instructions located in a memory unit are successively read out and executed. When an emergency task to be processed through the use of the central processing unit arises due to some requirement in the execution of such a program, the program in execution is interrupted in such a manner that it may be resumed later, and control passes to the emergency processing program. This is commonly referred to as an interrupt. The interruption sources are classified into an external source such as, for example, completion of the operation of an input/output unit, clock information, an instruction from an operator or another computer, a fault or the like, and an internal source such as, for example, an overflow, write in an inhibit area, execution of an inhibit instruction, absence of a reference command, or the like.
In the case of the external source, an address (in which the instruction to be executed is located) may be input from the outside but, mainly in the case of the internal source, the address of the next instruction and other information are held and the program jumps to a fixed address for the interrupt.
By the way, the concurrent operation of a plurality of programs is called multiprocessing. This is a multiprocessor system in terms of hardware. The multiprocessor system is complicated in program but is widely used on account of large process capacity, minimization of system failure, and flexibility.
In the case of forming the multiprocessor system with microprocessors, it is desirable that a plurality of processors of the same pattern (that is, of the same LSI circuit configuration) be arranged. In this case, however, each processor is provided with a fixed address supply source operating in accordance with an old-for-new exchange process for obtaining the contents of a program counter and a status word register, for example, according to an interruption source. However, if the fixed address supply sources of the processors are to generate the same fixed address, the respective processors will access the same address in a memory unit.